As very-large-scale-integrated-circuits (VLSI circuits are scaled to smaller dimensions, continued improvement in device drive current is necessary. In a metal-oxide-semiconductor (MOS) device, drive current is determined, in part, by gate length, gate capacitance, and carrier mobility. At a given device size improved device current can be obtained by increasing the carrier mobility.
A widely used technique to enhance carrier mobility includes forming a strained silicon channel region. Strain or stress in the silicon lattice can enhance bulk electron and hole mobility through the crystalline lattice. The formation of a strained silicon region for fabrication of an MOS device channel is a relatively straight forward way to improve device performance without introducing process scaling complexity.
A common practice used to create strain in a silicon lattice is to form a layer of material adjacent to the silicon that has a lattice constant that differs from silicon. Both silicon germanium (SiGe) and silicon carbide (SiC) have been used in MOS device fabrication. Since the lattice constant of SiGe is larger than that of silicon, the lattice mismatch puts the silicon under tension and the charge carrier mobility increases though the strained silicon lattice. Similarly, the lattice constant of SiC differs from silicon, however, the type of strain created by SiC differs from that created by SiGe. Alloys such as SiGe create compressive strain in silicon, while SiC creates tensile strain in silicon. A bi-axial, in-plane tensile strain field can improve performance in n-type MOS devices, and compressive strain parallel to channel length direction can improve performance in p-type MOS devices.
In the case of silicon substrates, field effect transistors (FETs) are usually fabricated in silicon substrates having a <100> crystallographic surface orientation. In <100> silicon, the mobility of holes, which are the majority carrier in a p-channel FET (PFET), can be increased by applying a compressive longitudinal stress to the channel. A compressive longitudinal stress can be applied to the channel of FET by embedding SiGe in the silicon substrate at the ends of the transistor channel. As described above, an SiGe crystal has a greater lattice constant than the lattice constant of a silicon crystal, and consequently the presence of embedded SiGe causes a deformation of the silicon matrix that, in turn, compresses the silicon in the channel region.
In the manufacture of epitaxially grown embedded SiGe layers during semiconductor device fabrication, a cavity is typically created in the active area of the PFET device. The cavity is then filled with epitaxially grown SiGe material, which may be in-situ doped with a material such as boron. During the formation of an embedded SiGe structure, the SiGe may be overgrown in the cavity such that a facet is created at the edge of the active area of the transistor, adjacent a shallow trench isolation (STI) region. Such faceting can result undesirable junction leakage current, and adversely affects device performance.
Another method of increasing hole mobility in PMOS devices is to form a channel region including SiGe. This is typically accomplished by forming a compressively strained SiGe epitaxial layer (cSiGe) over silicon in the PMOS channel regions prior to forming the PMOS transistor gate. To fabricate the channel region, it is necessary to carefully control the epitaxially deposition process such that a cSiGe layer of precise thickness is formed. Overgrowth of SiGe can create current leakage paths in the channel region.
The formation of SiGe layers through the use of relatively straight forward epitaxial deposition processes creates strain that enhances carrier mobility in MOS devices. While epitaxial deposition techniques offer a ready means of forming SiGe, the epitaxial deposition can be difficult to control. As noted above, overgrowth of SiGe can have undesirable consequences on device performance and can lead to increased manufacturing costs if device substrates have to be discarded.